In low speed synchronous data communication systems, clock skew or propagation delay between subsystems is negligible relative to the data cycle time. In such systems, data sequentially transmitted at low speed from a first subsystem is stable long enough to allow a skewed clock to capture the data in a state device of a second subsystem while meeting the setup and hold time requirements of the state device.
At higher data rates, however, clock skew becomes an increasingly important factor. As the data rate increases, the amount of time each transmitted data unit is stable decreases. The minimum period of time for which data must be stable to ensure accurate transmission, depends on the amount of skew and the setup and hold times of the receiving state device. In conventional systems, the data is typically stable for at most one clock cycle. It is thus not possible to guarantee accurate data transfer if the clock skew or propagation delay between two subsystems exceeds one clock cycle.
Systems allowing high speed synchronous data communication between subsystems where the clock skew can exceed an entire clock cycle are disclosed in U.S. Pat. Nos. 4,811,364, 4,979,190, and 5,115,455, each of which is assigned to the Digital Equipment Corporation. Generally, in the systems disclosed therein, data synchronous to a first clock, is transferred from a transmitting subsystem to a receiving subsystem. The operation of the receiving subsystem is synchronous with a second clock which is local to the receiving subsystem. The first and second clocks are typically generated by a common clock generator. .Although they are assumed to have a fixed frequency relationship, the two clocks are assumed to have an unknown phase relationship by virtue of being subjected to different and unknown path delays.
In one embodiment, the first clock is forwarded with the data. The receiving subsystem uses the forwarded clock to capture each data bit received in one of two or more parallel state devices. Where there are N such parallel state devices, each is selected in a rotating order to capture every Nth bit of incoming data and to hold it for N cycles. The outputs of each state device, being thus stretched, are then sampled in the same rotational order in which the state devices are selected to capture the incoming data bits. The sampling is synchronous with the local clock of the receiving subsystem. Having been stretched to N cycles, each data bit received is thus held stable long enough to be accurately sampled using the local clock which can be skewed and delayed up to N cycles relative to the forwarded clock.
Delay and skew greater than N cycles, however, cannot be tolerated without increasing circuit complexity proportionately. Since the propagation delay for a signal is generally proportional to distance travelled, such synchronous data transmission systems thus have a theoretically finite operating range which depends on the value of N.